Intel Corporation, assignee of the present invention, has commercialized a global reset circuit of the general type to which the present invention is directed. This circuit is generally indicated by the reference 10 in FIG. 1 and is more specifically depicted within the dashed box in FIG. 3, that is, excluding the grounded resistor R1 shown outside the dashed box. Referring specifically to FIG. 1 in conjunction with FIG. 2, global reset circuit 10 is shown including an input 12 connected through an on/off switch 14 to a direct current supply voltage Vcc which also serves to power microprocessor 16 and other components 17 and 18, all of which along with circuit 10 are formed on die 19. While the reset circuit is shown separate from microprocessor 10, it could be integrated into the latter. As illustrated in FIG. 2A, the direct current power supply voltage Vcc, when activated by closing switch 14, rises from its minimum voltage level, specifically 0 volts, to a maximum amplitude Vm over a discrete period of time.
Still referring to FIG. 1 in conjuction with FIG. 2, global reset circuit 10 includes an output 20 connected with microprocessor 16 and components 17 and 18 for resetting certain ones of their circuits to specific logic levels when the reset circuit asserts itself by presenting a global reset signal at output 20. As will be described in more detail hereinafter in conjunction with FIG. 3, the global reset circuit includes internal circuitry responsive to the power supply voltage Vcc, as the latter rises from its minimum level, for providing the previously recited global reset signal at output 20 until the power supply voltage reaches a predetermined voltage level, less than its maximum level Vm, depicted as V.sub.trip, at which time the circuit de-asserts itself, removing the reset signal and allowing the microprocessor 16 and the other components on the die to operate without regard to circuit 10. The voltage level at which the global reset circuit de-asserts itself, for example voltage V.sub.trip, is selected to be at a substantially higher voltage level than voltage levels required to reliably reset the circuits in question. For example, reliable reset voltage levels might be on the order of 1.5 volts and the reset signal at output 20 of the global reset circuit may not be removed until power supply voltage Vcc reaches 3.0 volts. In that way, de-assertion of the global reset circuit (the point at which the reset signal is removed) is set sufficiently high to enable initialization procedures to take place at the microprocessor and the other components on the die before the reset circuit reaches its trip point.
While global reset circuit 10 operates in a generally satisfactory manner for its intended pupose, it has been found to sometimes respond adversely to brief interruptions in the power supply voltage Vcc, typically interruptions on the order of several seconds or less, after the appropriate circuits have been reset and the reset signal removed from output 20. Specifically, even when a very brief interruption in power supply voltage Vcc occurs at this time, upon the immediate return of the power supply voltage, global reset circuit 10 should function in the manner previously described, that is, to provide the necessary reset signal at output 20 in order to reset the appropriate circuits. However, if the interruption is sufficiently short, circuit 10 has been found not to function. That is, as the power supply voltage Vcc initially rises again, the reset signal should be present but is not and at the point at which the reset signal should be removed, it remains de-asserted. The reason for this will be described immediately below in conjunction with FIG. 3.
Referring briefly to FIG. 3, the previously commercialized reset circuit 10 (located within the dashed box) includes CMOS transistors MP2-MP3-MN3 which, as will be seen hereinafter, serve as a regenerative latching circuit for the overall circuit. More specifically, when the power supply voltage Vcc is initially powered-up, transistor MP1 turns on slowly and continues to do so for maintaining the overall circuit in its asserted state with the reset signal present at output terminal 20. During this time, the latching circuit is maintained in its unlatched state which is accomplished by turning MP2 off, MP3 on, and MN3 off, which results in PWR1 being low and PWR2 being high. When Vcc reaches the selected tripping level in order to remove the reset signal, transistor MP1 is gated off and latches in its off state so long as the power supply voltage remains at its operating level. This ensures the absence of a reset signal at output 20. This also places the latching circuit in its latched on state which is the reverse of the above, that is, MP2 is on, MP3 is off and MN3 is on. This last latched state must be reversed in order for the circuit to be ready for the next Vcc rise. In this case, PWR1 is left to leak off to O v reverse the latched state. This leakage is mainly reverse diode leakage, i.e., very slow. It is important to note that all the charge on PWR1 musk leak away (To O v) before the circuit 10 is ready for the next closure of switch 14. However, in those situations where the interruption is short, the gating voltage of transistor MP3 (the voltage level at PWR1) does not always have a chance to discharge completely. In this regard, it should be kept in mind that the previously commercialized global reset circuit 10 does not include the grounded resistor R1 which, as will be seen, is provided in accordance with the present invention. If indeed the gated voltage transistor MP3 does not have a chance to discharge during the interruption, there will be no reset pulse assertion.